1. FIELD OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device in which a self-align-silicide film of a refractory metal is formed on the diffusion layer and the gate electrode of a MOS transistor.
2. DESCRIPTION OF THE PRIOR ART
Semiconductor elements continue to shrink in line width and increase in density. At present, super-high-integrated semiconductor devices, such as a memory device or a logic device, which are designed by the size standard (design rule) of 0.15 to 0.25 .mu.m are manufactured. With high integration of semiconductor devices, decreases in widths of the gate electrode and the diffusion layer and a decrease in film thickness of each material layer constituting a semiconductor element have become increasingly important.
The decrease in width of the gate electrode or gate electrode interconnection and the decrease in film thickness of the gate electrode layer inevitably increase the resistances of the interconnections, greatly affecting the circuit delay. When conventional polysilicon is used as an electrode material and an interconnection material, the delay time increases to a non-negligible degree due to the increase in interconnection resistance. Therefore, in micropatterned semiconductor elements as described above, a technique of realizing lower-resistance gate electrodes and interconnections using a silicide of a refractory metal has become indispensable. Particularly, a technique of forming a salicide (self-align-silicide) using, e.g., titanium (Ti) as a refractory metal is important in the manufacturing process of a micropatterned MOS (Metal-Oxide-Semiconductor) transistor.
With further high integration of semiconductor devices, in an insulated gate field effect transistor represented by a MOS transistor, the short channel effect of the transistor must be suppressed by suppressing diffusion of the impurity used for forming the diffusion layer. As a result, if the junction surface of the diffusion layer contacts the silicide region layer, the leakage current due to crystal defects increases, and the switch operation of the transistor cannot be performed. Therefore, the film thickness of the silicide layer must be decreased in addition to realization of a shallow-junction diffusion layer.
A conventional method of manufacturing a MOS transistor having a salicide structure will be explained. FIGS. 1A to 1E are sectional views respectively showing the steps in an example (to be referred to the first conventional method hereinafter) of a conventional salicide formation method.
First, as shown in FIG. 1A, an oxide film serving as an element isolation insulating film 102 is formed in a predetermined region on a silicon substrate 101 by well-known LOCOS (LOCal Oxidation of Silicon). After an impurity for a channel stopper is ion-implanted, a gate insulating film 103 is formed by the thermal oxidation method. Subsequently, a polysilicon film having a film thickness of about 150 nm is formed on the entire surface by CVD (Chemical Vapor Deposition). After an impurity such as phosphorus is doped, this polysilicon film is patterned into a desired shape by the lithography technique and the dry etching technique to form a gate electrode 104 on the gate insulating film 103. A silicon oxide film is deposited on the entire surface using the CVD method and subjected to anisotropic dry etching to form a spacer (side wall) 105 on the side surface of the gate electrode 104. Then, an impurity such as arsenic (As) or boron (B) is doped, and a heat treatment is performed at 800.degree. C. to 1,000.degree. C. to form diffusion layers 106. In the case of an n-channel MOS transistor, arsenic-doped diffusion layers are formed, whereas in the case of a p-channel transistor boron-doped diffusion layers are formed. In either case, the diffusion layers on the two sides of the gate electrode 104 serve as the source and drain regions of the MOS transistor, respectively. In the example shown in FIG. 1A, the diffusion layer 106 on the right side of the gate insulating film 103 coincides with the ion-implanted region for the channel stopper.
As shown in FIG. 1B, a titanium film 107 having a film thickness of about 50 nm is formed on the entire surface by the sputtering method or the like. Upon this film formation, when the substrate is unloaded from the film formation unit and exposed to the outer atmosphere, the surface of the titanium film 107 oxidizes to form a titanium oxide film 108 having a thickness of about 5 nm.
The first heat treatment is performed in a nitrogen atmosphere at normal pressure for 30 sec to 60 sec to silicify the titanium film 107. In this heat treatment, a lamp annealer is normally used, and the heat treatment temperature is set at 600.degree. C. to 650.degree. C. The crystal structures of titanium silicide are classified into the C49 structure having a relatively high electrical resistivity, and the C54 structure having a relatively low electrical resistivity. In this case, as shown in FIG. 1C, silicide layers 109 of the C49 structure having a relatively high electrical resistivity are formed on the exposed surface of the gate electrode 104 and the surfaces of the diffusion layers 106, and titanium nitride layers 110 are formed on the uppermost surfaces. In contrast, oxygen-containing titanium layers 111 which contain unreacted oxygen are formed on the element isolation insulating film 102 and the spacer 105 which are formed of silicon oxide films, and titanium nitride layers 110 are formed on the uppermost surfaces. Further, the titanium film 107 reduces the silicon oxide films serving as the element isolation insulating film 102 and the spacer 105 to form titanium oxide films 108 at the interfaces between these silicon oxide films and the oxygen-containing titanium layers 111.
Next, the resultant structure is dipped in an etching solution mixture of an aqueous ammonia solution, pure water, and a hydrogen peroxide solution to remove the oxygen-containing titanium layers 111 containing unreacted oxygen, and the titanium nitride layers 110, as shown in FIG. 1D. Although the titanium film 107 is dissolved by the etching solution of this composition, the titanium nitride layers 110 are not dissolved by this etching solution but removed by the lift-off effect upon elution of the oxygen-containing titanium layers 111.
By the above steps, the silicide layers 109 of the C49 structure are formed in self-alignment only on the gate electrode 104 and the diffusion layers 106 for forming the source and drain regions. The resultant structure is subjected to the second heat treatment in a nitrogen atmosphere at normal pressure for about 60 sec to cause a crystal structure transition. That is, as shown in FIG. 1E, the silicide layers 109 of the C49 structure are converted into silicide layers 112 of the C54 structure having a relatively low electrical resistivity. As a heat treatment unit at this time, a lamp annealer is used, like in the first heat treatment. The process temperature is set at about 850.degree. C. In this manner, a silicide layer of the C54 structure used as the electrode layer of a semiconductor device can be formed in self-alignment.
On the other hand, Japanese Unexamined Patent Publication No. 63-50038 discloses a method characterized by performing the film formation step of a refractory metal film and the heat treatment step "in situ". This method uses an equipment including a sputtering unit, an electrical furnace unit, and a unit for keeping the respective units in vacuum via an exhaust unit, and the step of forming a refractory metal film by sputtering and the silicification step are continuously executed without exposing the structure to the outer atmosphere. According to this method, a heat treatment for silicification can be executed without forming any oxide layer on the surface of the refractory metal film formed by sputtering. Although Japanese Unexamined Patent Publication No. 63-50038 discloses an example using tungsten (W) or molybdenum (Mo) as the refractory metal, a case wherein the technique disclosed in Japanese Unexamined Patent Publication No. 63-50038 is applied to formation of a titanium silicide film will be explained below. FIGS. 2A to 2E are sectional views respectively showing the steps in a salicide formation method (to be referred to as the second conventional method hereinafter).
The respective steps from formation of a MOS transistor to formation of a titanium film by the sputtering method are performed similar to those in the first conventional method described above. That is, as shown in FIG. 2A, a 300 nm-thick element isolation insulating film 102 is formed by the LOCOS method in a predetermined region on a silicon substrate 101 which is of p-type or has a p-well formed therein. Boron for a channel stopper is ion-implanted in the silicon substrate 101 to form a gate insulating film 103 having a film thickness of about 8 nm by the thermal oxidation method. A polysilicon film having a film thickness of about 100 nm is formed on the entire surface by the CVD method. After an impurity such as phosphorus is doped, this polysilicon layer is patterned by the lithography technique and the dry etching technique to form a gate electrode 104. After a silicon oxide film is deposited on the entire surface by the CVD method to have a film thickness of about 100 nm, anisotropic dry etching is performed to form a spacer 105 on the side surface of the gate electrode 104. Thereafter, diffusion layers 106 are formed by ion implantation of an arsenic impurity.
Next, as shown in FIG. 2B, a titanium film 107 having a thickness of about 20 nm is formed on the entire surface by, e.g., the sputtering method using argon gas. The resultant structure is subjected to a heat treatment in a nitrogen atmosphere without being exposed to the outer atmosphere, thereby forming silicide layers 109 of the C49 structure on the silicon exposed surfaces (FIG. 2C). Since the structure is not exposed to the outer atmosphere, no titanium oxide is formed on the surface of the titanium film 107, and heat treatment of the titanium film 107 can be performed. However, similar to the first conventional method described above, titanium oxide films 108 are formed at the interfaces between the element isolation insulating film 102 and the spacer 105, and the titanium film 107 due to reduction by the titanium film 107. For this reason, as shown in FIG. 2D, a titanium nitride layer 110 and the non-silicified titanium film 107 are removed by an aqueous ammonia solution, and a heat treatment is performed to convert the silicide layers 109 of the C49 structure into silicide layers 112 of the C54 structure having a lower resistivity (FIG. 2E).
In either of the above-mentioned conventional methods, in heat treatment upon film formation of the titanium film, titanium oxide films are formed due to reduction by titanium at the interfaces between the titanium film, and the element isolation insulating film and the spacer which are made of silicon oxide films. As will be described in detail later, this titanium oxide film cannot be removed by an etching solution containing an aqueous ammonia solution as a component, and further exhibits semiconductor properties. For this reason, the titanium oxide film causes a leakage current across the gate electrode and the diffusion layer regions and poses a problem in processing.
According to the first conventional method, by a heat treatment in the nitrogen atmosphere, the titanium film on the silicon oxide film has a three-layered structure of a titanium nitride layer, an oxygen-containing titanium layer, and a titanium oxide film. A detailed mechanism of this structure is as follows. That is, in this heat treatment step, the surface oxygen concentration of the titanium film decreases due to reduction by nitrogen, and as the nitride film is formed, oxygen diffuses into the titanium film to form an oxygen-containing titanium layer. The snowplow effect of oxygen due to nitridation by nitrogen (N.sub.2 gas) becomes dominant, while reduction of the titanium oxide film becomes deficient. As a result of this oxygen diffusion, the titanium film on the silicon oxide film has a three-layered structure of a titanium nitride layer, an oxygen-containing titanium layer containing a large amount of oxygen, and a titanium oxide film.
After heat treatment, the titanium film is selectively etched. In selective etching, the oxygen-containing titanium layer remaining on the silicon oxide film is etched by using a solution mixture of ammonia and a hydrogen peroxide solution, thereby removing the titanium nitride layer by the lift-off effect. However, the etching rate of the oxygen-containing titanium layer decreases with an increase in oxygen concentration. The titanium oxide film is not etched by the solution mixture of ammonia and the hydrogen peroxide solution. Although the titanium oxide film may be etched by prolonging the etching time and increasing the solution temperature, since the etching rate of the silicide layer of the C49 structure also increases, the selectivity is not actually improved. As a result, it is difficult to remove the titanium oxide film.
According to the second conventional method, film formation of the titanium film and a heat treatment are continuously performed without exposing the structure to the outer atmosphere. In this case, since oxygen diffusion due to nitridation does not take place, no oxygen-containing titanium layer is formed. However, a titanium oxide film generated due to reduction by titanium still exists, which causes a leakage current.
FIGS. 3A and 3B are graphs of frequency distributions respectively showing the measurement results of the leakage current across the gate electrode and the diffusion layer in a large number of MOS transistors formed by the above-described conventional methods. FIG. 3A shows the result obtained in the MOS transistor according to the first conventional method, and FIG. 3B shows the result obtained in the MOS transistor according to the second conventional method. As is apparent from the two graphs, the frequency of the leakage current in the second method is lower than that in the first method, but in either case a leakage current of 10.sup.-6 A or more flows, which cannot be ignored in relation to the OFF current of the transistor.